Voltage regulators have been widely used in various electronic devices to implement the power supplies for providing stable supply voltages for the circuits in the electronic devices. However, spike will be generated on the output voltage of the voltage regulator in load transient resulted from instant load change, and large voltage spike may damage the load connected to the voltage regulator. FIG. 1 is a waveform diagram to show the output signals of a conventional voltage regulator in a load transient, in which waveform 100 represents the load current ILoad and waveform 102 represents the output voltage Vout. At time t1, in response to the load changing from light to heavy, the load current ILoad steps up, and the output voltage Vout drops down from the nominal voltage by a difference ΔV and then gradually recovers to the original level. At time t2, the load changes from heavy back to light and therefore, the load current ILoad steps down, and the output voltage Vout jumps up from the nominal voltage by the difference ΔV and then recovers back to the original level. As shown in FIG. 1, the output voltage Vout has a spike having the amplitude 2ΔV due to the load transient. To avoid the voltage spike so large to damage the load, conventionally several parallel-connected capacitors are used at the output of a voltage regulator to reduce the voltage spike. However, increasing the size of the output capacitor will increase the volume, weight and cost of the voltage regulator. It is therefore a stringent challenge on the voltage regulator module (VRM) for real applications. To alleviate this problem, Intel has proposed an adaptive voltage position (AVP) control, which uses a voltage droop control in a voltage regulator to reduce the voltage spike on the output voltage of the voltage regulator. FIG. 2 is a waveform diagram to show the output signals when the AVP control is applied in a voltage regulator, in which waveform 104 represents the load current ILoad and waveform 106 represents the output voltage Vout. When the load changes from light to heavy at time t1, the load current ILoad steps up and the output voltage Vout drops down by a difference ΔV, as in the conventional one 102. However, under the AVP control, the output voltage Vout is maintained at the lower level once it drops down, and until the load changes from heavy back to light, the output voltage Vout recovers from the low level back to the nominal voltage. As shown in FIG. 2, the spike of the output voltage Vout due to the same load transient is much smaller than 2ΔV of the conventional one 102, and thus the AVP control significantly reduces the voltage spike resulted from the load transient.
Intel's road map shows that the VRM for central processing unit (CPU) needs very tight regulation. Currently, active droop control is a popular way to achieve the AVP of a VRM, and an implementation is based on a low-gain peak current-mode topology. FIG. 3 shows a current-mode voltage regulator 110, which comprises an error amplifier 112 having a gain Av to amplify the difference between the output voltage Vout of the voltage regulator 110 and a reference voltage Vref to produce an error signal COMP connected to the inverting input of a pulse-width modulation (PWM) comparator 114, and a voltage amplifier 116 having a gain Ai to detect the inductor current IL flowing through an inductor L to produce a current sense signal VCS connected to the non-inverting input of the PWM comparator 114 for the PWM comparator 114 to compare with the error signal COMP to determine a PWM signal connected to the reset input R of an SR flip-flop 118 that has its set input S connected with a constant-frequency clock CLK. Upon the clock CLK transiting from low level to high level, the SR flip-flop 118 is triggered to set its output Q for a high-side switching signal U to be high level and complementary output /Q for a low-side switching signal L to be low level, and upon the PWM signal transiting from low level to high level, which is when the current sense signal VCS is crossing with the error signal COMP, the SR flip-flop 118 is reset to transit the high-side switching signal U from high level to low level and the low-side switching signal L from low level to high level. The switching signals U and L switch a high-side transistor 124 and a low-side transistor 126 with two driver 120 and 122, respectively, to produce the inductor current IL to charge an output capacitor C having an equivalent series resistance Resr thereof to thereby obtain the output voltage Vout. When the load current ILoad stays high, the output voltage Vout will be at the lower level, as illustrated by FIG. 2, and when the load current ILoad steps back down, the output voltage Vout will spike up byΔV=ILoad×Resr×Ai/Av  [EQ-1]Unfortunately, in a low-gain current PWM mode, the gain Av of the error amplifier 112 may be too small to reduce the ripple effect of the current sense signal VCS and error signal COMP, and there will be thus an offset occurred in the output voltage Vout of the voltage regulator 110. Namely, the low-gain current-mode voltage regulator is inherently disadvantageous because of the output offset. FIG. 4 shows the current sense signal VCS and error signal COMP in a PWM on-time period when the error amplifier 112 has a small gain Av, in which waveform 130 represents the error signal COMP and waveform 132 represents the current sense signal VCS. When the high-side transistor 124 is on, the current sense signal VCS raises up and the error signal COMP falls down. As the current sense signal VCS is crossing with the error signal COMP, the high-side transistor 124 will turn off and the output voltage Vout will decrease. Accordingly, the error signal COMP raises up and the current sense signal VCS falls down. The loop so operates cycle by cycle. Due to the ripple effect of the error signal COMP and current sense signal VCS, as shown in FIG. 4, the output voltage Vout will have an offset apart from the reference voltage Vref in the magnitude of
                                                        Vout              ,                              offset                =                                ⁢                                  Voffset                  /                  Av                                                                                                        =                            ⁢                                                (                                                            Δ                      ⁢                                                                                          ⁢                      V                      ⁢                                                                                          ⁢                      1                                        +                                          Δ                      ⁢                                                                                          ⁢                      V                      ⁢                                                                                          ⁢                      2                                                        )                                /                Av                                                                                        =                            ⁢                                                1                  2                                ⁢                                                      (                                                                  Δ                        ⁢                                                                                                  ⁢                        IL                        ×                        Re                        ⁢                                                                                                  ⁢                        sr                        ×                        Av                                            +                                              Δ                        ⁢                                                                                                  ⁢                        IL                        ×                        Rs                        ×                        Ai                                                              )                                    Av                                                                                                        =                            ⁢                                                1                  2                                ⁡                                  [                                                                                                              Vi                          ⁢                                                                                                          ⁢                          n                                                -                        Vout                                            L                                        ×                    Ton                    ×                                          (                                              Resr                        +                                                  Rs                          ×                                                      Ai                            Av                                                                                              )                                                        ]                                                                                                        =                            ⁢                                                1                  2                                [                                                                                                    Vi                        ⁢                                                                                                  ⁢                        n                                            -                      Vout                                        L                                    ×                                      Vout                                          Vi                      ⁢                                                                                          ⁢                      n                                                        ×                  T                  ×                                                                                                                      ⁢                              (                                  Resr                  +                                      Rs                    ×                                          Ai                      Av                                                                      )                            ]                                                          [                  EQ          ⁢                      -                    ⁢          2                ]            where ΔV1 is the amplitude of the error signal COMP, ΔV2 is the amplitude of the current sense signal VCS, ΔIL is the ripple amplitude of the inductor current IL, Rs is the resistance of the current sense resistor Rs serially connected to the inductor IL, Ton is the on-time of the high-side transistor 124, and T is the switching period of the high-side transistor 124 and low-side transistor 126. Since the parameters L, T, Resr, Rs, Av and Ai are all constant, it may be obtained from the equation EQ-2 the relation
                    Voffset        ∝                              (                                          Vi                ⁢                                                                  ⁢                n                            -              Vout                        )                    ×                      Vout                          Vi              ⁢                                                          ⁢              n                                                          [                  EQ          ⁢                      -                    ⁢          3                ]            which shows the reason why the output voltage Vout will not be equal to the reference voltage Vref when the inductor current IL is zero.
Therefore, it is desired to cancel the low-gain system offset of a current-mode voltage regulator.